? 2003 microchip technology inc. ds80132c-page 1 ssp module the picmicro ? microcontrollers you have received all exhibit anomalous behavior in their synchronous serial port (ssp) modules, as described in this document. they otherwise conform functionally to the descriptions provided in their respective device data sheets and reference manuals, as amended by silicon release errata for particular devices. users are encouraged to review the latest device data sheets and errata available for additional information concerning an individual device. these documents may be obtained directly from the microchip corporate web site, at www.microchip.com . this issue is expected to be resolved in future silicon revisions of the designated parts. this issue effects all silicon revisions of the following devices: 1. issue: i 2 c? (slave mode) in its current implementation, the module may fail to correctly recognize certain repeated start conditions. for this discussion, a repeated start is defined as a start condition presented to the bus after an initial valid start condition has been recognized and the start status bit (sspstat<3>) has been set, and before a valid stop condition is received. if a repeated start is not recognized, a loss of synchronization between the master and slave may occur; the condition may continue until the module is reset. a nack condition, generated by the slave for any reason, will not reset the module. this failure has been observed only under two circumstances: a repeated start occurs within the frame of a data or address byte. the unexpected start condition may be erroneously inter- preted as a data bit, provided that the required conditions for setup and hold times are met. a repeated start condition occurs between two back-to-back slave address matches in the same slave, with the r/w bit set to read (= 1 ) in both cases. (this circum- stance is regarded as being unlikely in normal operation.) work around a time-out routine should be used to monitor the module's operation. the timer is enabled upon the receipt of a valid start condition; if a time-out occurs, the module is reset. the length of the time- out period will vary from application to application, and will need to be determined by the user. two methods are suggested to reset the module: 1. change the mode of the module to something other than the desired mode by changing the settings of bits sspm3:sspm0 (sspcon<3:0>); then, change the bits back to desired configuration. 2. disable the module by clearing the sspen bit (sspcon<5>); then, re-enable the module by setting the bit. other methods may be available. pic14000 pic16c74a pic16c62a pic16c74b pic16c62b pic16c76 pic16c63 pic16c77 pic16c63a pic16c923 pic16cr63 pic16c924 pic16c64a pic16c925 pic16c65a pic16c926 pic16c65b pic16f72 pic16cr65 pic16f73 pic16c66 pic16f74 pic16c67 pic16f76 pic16c72 pic16f77 pic16c73a PIC16F818 pic16c72a pic16f819 pic16c73b ssp module silicon/data sheet errata
ssp module ds80132c-page 2 ? 2003 microchip technology inc. clarifications/corrections to the data sheets 1. module: ssp (spi mode) the description of the operation of the cke bit (sspstat<6>) is clarified. please substitute the description in register 1, below, for all occurrences of the existing text for the sspstat register, bit 6 (new text in bold ). 2. module: ssp (spi slave mode) the description of the operation of spi slave mode is clarified as follows: before enabling the module in spi slave mode, the state of the clock line (sck) must match the polarity selected for the idle state. the clock line can be observed by reading the sck pin. the polarity of the idle state is determined by the ckp bit (sspcon<4>). this foregoing text should be added to the appropriate subsections of the ?ssp module? chapter entitled ?spi mode?, and read in context with any discussions of spi slave mode. in the case of ds30234d, the text applies to both implementations of spi mode, as described in sections 11.2 and 11.3. register 1: sspstat: ssp status register (excerpt) note: this correction applies to the data sheets for the following devices: pic16c62b/72a (ds35008b) pic16c63a/65b/73b/74b (ds30605c) pic16c923/924 (ds30444e) pic16c925/926 (ds39544a) pic16f72 (ds39597b) pic16f73/74/76/77 (ds30325b) PIC16F818/819 (ds39598c) in addition, this clarification applies only to the following devices in the pic16c6x data sheet (ds30234d): pic16c66 pic16c67 any devices not explicitly listed in this sec- tion do not implement spi mode, and are not affected by this clarification. note: this text refers only to the operation of the cke bit in spi mode; its operation in i 2 c mode is unchanged. note: this correction applies to the data sheets for the following devices: pic16c6x (ds30234d), except pic16c61 (does not implement the ssp module) pic16c62b/72a (ds35008b) pic16c63a/65b/73b/74b (ds30605c) pic16c923/924 (ds30444e) pic16c925/926 (ds39544a) pic16f72 (ds39597b) pic16f73/74/76/77 (ds30325b) PIC16F818/819 (ds39598c) any other devices not explicitly listed in this section do not implement spi mode, and are not affected by this clarification. bit 6 cke: spi clock select bit 1 = transmit occurs on transition from active to idle clock state 0 = transmit occurs on transition from idle to active clock state note: polarity of clock state is set by the ckp bit (sspcon<4>).
? 2003 microchip technology inc. ds80132c-page 3 ssp module revision history revision a document (7/2002): original version (i 2 c slave issue) revision b document (1/2003): clarification of original issue to include restart conditions. addition of data sheet clarification 1 (spi mode, cke bit). revision c document (3/2003): addition of data sheet clarification 2 (spi slave mode, operation).
ssp module ds80132c-page 4 ? 2003 microchip technology inc. notes:
? 2003 microchip technology inc. ds80132c - page 5 information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. it is your responsibility to ensure that your application meet s with your specifications. no representation or warranty is giv en and no liability is assumed by microchip technology incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. use of microchip?s products as critical components in life support systems is not authorized except with express written approval by microchip. no licens es are conveyed, implicitly or otherwise, under any intellectual property rights. trademarks the microchip name and logo, the microchip logo, k ee l oq , mplab, pic, picmicro, picstart, pro mate and powersmart are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. filterlab, micro id , mxdev, mxlab, picmaster, seeval and the embedded control solutions company are registered trademarks of microchip technology incorporated in the u.s.a. accuron, application maestro, dspic, dspicdem, dspicdem.net, economonitor, fansense, flexrom, fuzzylab, in-circuit serial programming, icsp, icepic, microport, migratable memory, mpasm, mplib, mplink, mpsim, picc, pickit, picde m, picdem.net, powercal, powerinfo, powermate, powertool, rflab, rfpic, select mode, smartsensor, smartshunt, smarttel and total endurance are trademarks of microchip technology incorporated in the u.s.a. and other countries. serialized quick turn programming (sqtp) is a service mark of microchip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 2003, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. microchip received qs-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona in july 1999 and mountain view, california in march 2002. the company?s quality system processes and procedures are qs-9000 compliant for its picmicro ? 8-bit mcus, k ee l oq ? code hopping devices, serial eeproms, microperipherals, non-volatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001 certified. note the following details of the code protection feature on microchip devices: microchip products meet the specification cont ained in their particular microchip data sheet. microchip believes that its family of products is one of the mo st secure families of its kind on the market today, when used i n the intended manner and under normal conditions. there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the micr ochip products in a manner outside the operating specifications containe d in microchip's data sheets. most likely, the person doing so is engaged in theft of intellectual property. microchip is willing to work with the customer who is concerned about the integrity of their code. neither microchip nor any other semiconductor manufacturer c an guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are co mmitted to continuously improvi ng the code protection features of our products. attempts to break microchip?s c ode protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act.
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